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MDT10P712
1. General Description This EPROM-Based 8-bit micro-controller uses a fully static CMOS technology process to achieve higher speed and smaller size with the low power consumption and high noise immunity. On chip memory includes 1K words of ROM, and 128 bytes of static RAM. converter -8-bit resolution TMR0: 8-bit real time clock/counter TMR1: 16-bit real time clock/counter TMR2: 8-bit clock/counter 4 types of oscillator can be selected by programming option: RCLow cost RC oscillator LFXTLow frequency crystal oscillator XTALStandard crystal oscillator HFXTHigh frequency crystal oscillator
2. Features The followings are some of the features on the hardware and software: On-chip RC oscillator based Watchdog Fully CMOS static design Timer (WDT) 8-bit data bus 13 I/O pins with their own independent On chip EPROM size: 1.0 K words direction control Internal RAM size: 128 bytes 37 single word instructions 14-bit instructions 3. Applications 8-level stacks The application areas of this MDT10P712 Operating voltage:2.5V~5.5V(PRD disable) range from appliance motor control and high 4.5V~5.5V(PRD enable) speed auto-motive to low power remote Operating frequency: DC ~ 20 MHz transmitters/receivers, pointing devices, and The most fast execution time is 200 ns telecommunications processors, such as under 20MHz in all single cycle Remote controller, small instruments, chargers, instructions except the branch instruction toy, automobile and PC peripheral ... etc. Addressing modes include direct, indirect and relative addressing modes Power-on Reset Power edge-detector Reset Power range-detector Reset Sleep Mode for power saving Capture, Compare, PWM module 7 interrupt sources: -External INT pin -TMR0 timer, TMR1 timer, TMR2 timer -A/D conversion completion -PortB<7:4> interrupt on change -CCP A/D converter module: -4 analog inputs multiplexed into one A/D
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P. 1
Preliminary 2007/8
Ver1.0
MDT10P712
4. Pin Assignment 18-pin PDIP/SOP PA2/AIC2 1 18 PA1/AIC1 PA3/AIC3/Vref PA4/RTCC /MCLR VSS PB0/INT PB1/T1OSO/T1CKI PB2/T1OSI PB3/CCP 2 3 4 5 6 7 8 9 17 16 15 14 13 12 11 10 PA0/AIC0 OSC1 OSC2 VDD PB7 PB6 PB5 PB4 20-pin SSOP PA2/AIC2 1 20 PA1/AIC1 PA3/AIC3/Vref PA4/RTCC /MCLR VSS VSS PB0/INT PB1/T1OSO/T1CKI PB2/T1OSI PB3/CCP 2 3 4 5 6 7 8 9 10 19 18 17 16 15 14 13 12 11 PA0/AIC0 OSC1 OSC2 VDD VDD PB7 PB6 PB5 PB4
5. Pin Function Description Pin Name PA0~PA3 PA4/RTCC PB0~PB7 /MCLR OSC1/CLKIN OSC2/CLKOUT VDD VSS I/O I/O I/O I/O I I O Function Description Port A, TTL input level, Analog input channel. Real Time Clock/Counter, Schmitt Trigger input level. Open drain output. Port B, TTL input level, PB0: External Interrupt input. PB4~PB7: Interrupt on pin change. Master Clear, Schmitt Trigger input level. Oscillator Input, External clock input. Oscillator Output, In RC mode, the CLKOUT pin has 1/4 frequency of CLKIN. Power supply Ground
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P. 2
Preliminary 2007/8
Ver1.0
MDT10P712
6. Memory Map (A) Register Map Address BANK0 00 01 02 03 04 05 06 07 0A 0B 0C 0E 0F 10 11 12 15 16 17 1E 1F 20~7F BANK1 81 85 86 87 8C 8E TMR CPIO A CPIO B CPIOCCP PIEB1 PSTA Indirect Addressing Register RTCC PCL STATUS MSR Port A Port B DATACCP PCHLAT INTS PIFB1 TMR1L TMR1H T1STA TMR2 T2STA CCPL CCPH CCPCTL ADRES ADS0 General purpose register Description
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P. 3
Preliminary 2007/8
Ver1.0
MDT10P712
Address 92 9F A0~BF T2PER ADS1 General purpose register Description
(1) IAR (Indirect Address Register): R00 (2) RTCC (Real Time Counter/Counter Register): R01 (3) PC (Program Counter): R02, R0A Write PC --- from PCHLAT Write PC --- from PCHLAT LJUMP, LCALL --- from instruction word RTWI, RET --- from STACK A12~A11 A10~A8 A7~A0
Write PC --- from ALU LJUMP, LCALL --- from instruction word RTWI, RET, RTFI --- from STACK
(4) STATUS (Status register): R03 Bit 0 1 2 3 4 5 Symbol C HC Z PF TF RBS0 Carry bit Half Carry bit Zero bit Power down Flag bit WDT Timer overflow Flag bit Register Bank Select bit: 0: 00H --- 7FH (Bank0) 1: 80H --- FFH (Bank1) 7-6 ---- General purpose bit Function
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P. 4
Preliminary 2007/8
Ver1.0
MDT10P712
(5) MSR (Memory Bank Select Register): R04 Memory Bank Select Register: 0: 00~7F (Bank0) 1: 80~FF (Bank1) b7 b6 b5 b4 b3 b2 b1 b0
Indirect Addressing Mode (6) PORT A: R05 PA4~PA0, I/O Register (7) PORT B: R06 PB7~PB0, I/O Register (8) DATACCP: R07 Bit 0 1 2 7~3 Symbol DT1CK -DCCP -Unimplemented CCP1 PIN. Controlled from software. Unimplemented Function T1CKI PIN. Controlled from software.
(9) PCHLAT: R0A (10) INTS (Interrupt Status Register): R0B Bit 0 1 2 3 4 5 6 7 Symbol RBIF INTF TIF RBIE INTS TIS PEIE GIS Function PORTB<7~4> pin change interrupt flag. Set when INT interrupt occurs. INT interrupt flag. Set when TMR0 overflows. 0: disable PB change interrupt. 1: enable PB change interrupt. 0: disable INT interrupt. 1: enable INT interrupt. 0: disable TMR0 interrupt. 1: enable TMR0 interrupt. 0: disable all peripheral interrupt. 1: enable all peripheral interrupt. 0: disable global interrupt. 1: enable global interrupt.
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P. 5
Preliminary 2007/8
Ver1.0
MDT10P712
(11) PIFB1 (Peripheral Interrupt Flag Bit): R0C Bit 0 Symbol TMR1IF TMR1 interrupt flag 0: TMR1 did not overflow 1: TMR1 overflowed TMR2IF TMR2 interrupt flag 0: No TMR2 to T2PER match occurred 1: TMR2 to T2PER match occurred CCPIF CCP interrupt flag 0: No TMR1 capture/compare occurred 1: A TMR1 capture/compare occurred Unimplemented A/D interrupt flag 0: A/D conversion is not complete 1: A/D conversion completed Unimplemented Function
1
2
5~3 6
-ADIF
7
--
(12) TMR1L: R0E The LSB of the 16-bit TMR1 (13) TMR1H: R0F The MSB of the 16-bit TMR1 (14) T1STA: R10 Bit 0 1 2 Symbol TMR1ON 0: Stop TMR1. 1: enable TMR1. TMR1CLK 0: Internal clock (Fosc/4). 1: External clock from pin PB2. /T1SYNC TMR1CLK = 1 0: Synchronize external clock. 1: Do not synchronize external clock. TMR1CLK = 0 This bit is ignored. T1OSCEN 0: TMR1 Oscillator is shut off. 1: TMR1 Oscillator is enable. Function
3
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P. 6
Preliminary 2007/8
Ver1.0
MDT10P712
Bit Symbol Function
5~4 T1CKPS1 1 1 = 1:8 Prescale value ~ 1 0 = 1:4 Prescale value T1CKPS0 0 1 = 1:2 Prescale value 0 0 = 1:1 Prescale value 7~6 -Unimplemented (15) TMR2: R11 TMR2 register (16) T2STA: R12 Bit Symbol Function 1~0 T2CKPS1 0 0 = Prescaler is 1 ~ 0 1 = Prescaler is 4 T2CKPS0 1 x = Prescaler is 16 2 7~3 TMR2ON 0: TMR2 is on. 1: TMR2 is off. -Unimplemented
(17) CCPL: R15 Capture/Compare/PWM LSB (18) CCPH: R16 Capture/Compare/PWM MSB (19) CCPCTL: R17 Bit 3~0 Symbol Function CCPM3 0 0 0 0: CCP off. ~ 0 1 0 0: Capture mode, every falling edge. CCPM0 0 1 0 1: Capture mode, every rising edge. 0 1 1 0: Capture mode, every 4th rising edge. 0 1 1 1: Capture mode, every 16th rising edge. 1 0 0 0: Compare mode, set output on match. 1 0 0 1: Compare mode, clear output on match. 1 0 1 0: Compare mode, generate software interrupt on match. 1 0 1 1: Compare mode, trigger special event. 1 1 x x: PWM mode. 5~4 PWMLSB These bits are the two LSBs of the PWM duty cycle. 7~6 -Unimplemented
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P. 7
Preliminary 2007/8
Ver1.0
MDT10P712
(20) ADRES ( A/D result register ) : R1E (21) ADS0 ( A/D Status Register ) : R1F Bit 0 Symbol ADRUN Function 0: A/D converter module is shut off and consumes no operating current. 1: A/D converter module is operating. Unimplemented
1 2 5~3 7~6
--
GO/DONEB 0: A/D conversion in progress. 1: A/D conversion not in progress. CHS2~0 ASCS1-0 000: AIC0, 001: AIC1, 010: AIC2, 011: AIC3 00: fosc/2, 01: fosc/8, 10: fosc/32, 11: f RC (*Note)
*Note: determined by OSC mode, HF: fosc/32, XT: fosc/8, RC: fosc/2, LF: fosc/2 (22) TMR (Time Mode Register): R81 Bit Symbol Prescaler Value Function RTCC rate WDT rate 000 1: 2 1: 1 001 1: 4 1: 2 010 1: 8 1: 4 011 1: 16 1: 8 100 1: 32 1: 16 101 1: 64 1: 32 110 1: 128 1: 64 111 1: 256 1: 128 Prescaler assignment bit: 0: RTCC 1: Watchdog Timer RTCC signal Edge: 0: Increment on low-to-high transition on RTCC pin. 1: Increment on high-to-low transition on RTCC pin. RTCC signal set: 0: Internal instruction cycle clock. 1: Transition on RTCC pin. Interrupt edge select: 0: Interrupt on falling dege on PB0. 1: Interrupt on rising edge on PB0. PORTB pull-hi: 0: PORTB pull-hi enable. 1: PORTB pull-hi disable.
2~0
PS2~0
3
PSC
4
TCE
5
TCS
6
IES
7
PBPH
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P. 8
Preliminary 2007/8
Ver1.0
MDT10P712
(23) CPIO A (Control Port I/O Mode Register): R85 "0", I/O pin in output mode. "1", I/O pin in input mode. (24) CPIO B (Control Port I/O Mode Register): R86 "0", I/O pin in output mode. "1", I/O pin in input mode. (25) CPIOCCP: R87 Bit 0 1 2 7~3 Symbol CT1CK -CCCP -0: T1CKI pin is an output. 1: T1CKI pin is an input. Unimplemented 0: Output pin driven. 1: Output pin tristated. Unimplemented Function
(26) PIEB1: R8C Bit 0 Symbol TMR1IE TMR1 interrupt enable bit 0: disable TMR1 interrupt. 1: enable TMR1 interrupt. TMR2IE TMR2 interrupt enable bit 0: disable TMR2 interrupt. 1: enable TMR2 interrupt. CCPIE CCP interrupt enable bit 0: disable CCP interrupt. 1: enable CCP interrupt. Unimplemented A/D interrupt enable bit 0: disable A/D interrupt. 1: enable A/D interrupt. Unimplemented Function
1
2
5~3 6
-ADIE
7
--
(27) PSTA: R8E Bit 0 1 Symbol PRDB PORB Function 0: Power range-detector Reset occurred. 1: No Power range-detector Reset Occurred. 0: Power on Reset occurred. 1: No Power on Reset occurred.
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P. 9
Preliminary 2007/8
Ver1.0
MDT10P712
(28) T2PER: R92 Timer2 period (29) ADS1 (A/D Status Register): R9F Bit 2~0 Symbol Function 0 x 0: PA0~3= analog input. VREF= VDD. PAVM2~0 0 x 1: PA0~2= analog input. PA3= ref input. VREF= PA3. 1 0 0: PA0, 1, 3= analog input. PA2= digital I/O. VREF= VDD. 1 0 1: PA0, 1= analog input. PA2= digital I/O, PA3= ref input, VREF= PA3. 1 1 x: PA0~3= digital I/O. (30) Configurable options for EPROM (Set by writer): Oscillator Type RC Oscillator
HFXT Oscillator XTAL Oscillator LFXT Oscillator Watchdog Timer control Watchdog timer disable all the time Watchdog timer enable all the time Power-range control Power-range disable Power-range enable Oscillator-start Timer control 0ms 80ms Power-edge Detect PED Disable PED Enable Security state Security Disable Security Enable
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P. 10
Preliminary 2007/8
Ver1.0
MDT10P712
(B) Program Memory Address 000-3FF 000 004 Program memory The starting address of power on, external reset or WDT time-out reset. Interrupt vector Description
7. Reset Condition for all Registers Power-On Reset, Register Address Power range detector Reset IAR RTCC PCL STATUS MSR PORT A PORT B DATACCP PCHLAT INTS PIFB1 TMR1L TMR1H T1STA TMR2 T2STA CCPL CCPH CCPCTL ADRES ADS0 TMR CPIOA CPIOB 00h 01h 02h 03h 04h 05h 06h 07h 0Ah 0Bh 0Ch 0Eh 0Fh 10h 11h 12h 15h 16h 17h 1Eh 1Fh 81h 85h 86h N/A xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx ---x xxxx xxxx xxxx ---- -x-x ---0 0000 0000 000x -0-- 0000 xxxx xxxx xxxx xxxx --00 0000 0000 0000 ---- -000 xxxx xxxx xxxx xxxx --00 0000 xxxx xxxx 0000 00-0 1111 1111 ---1 1111 1111 1111
/MCLR or WDT Reset N/A uuuu uuuu 0000 0000 000# #uuu uuuu uuuu ---u uuuu uuuu uuuu ---- -u-u ---0 0000 0000 000u -0-- 0000 uuuu uuuu uuuu uuuu --uu uuuu 0000 0000 ---- -uuu uuuu uuuu uuuu uuuu --00 0000 uuuu uuuu 0000 00-0 1111 1111 ---1 1111 1111 1111
Wake-up from SLEEP N/A uuuu uuuu PC+1 000# #uuu uuuu uuuu ---u uuuu uuuu uuuu ---- -u-u ---u uuuu uuuu uuuu -u-- uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu ---- -uuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uu-u uuuu uuuu ---u uuuu uuuu uuuu
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P. 11
Preliminary 2007/8
Ver1.0
MDT10P712
Register CPIOCCP PIEB1 PSTA T2PER ADS1 Address 87h 8Ch 8Eh 92h 9Fh Power-On Reset, Power range detector Reset xxxx x1x1 -0-- 0000 ---- --0u 1111 1111 ---- -000 /MCLR or WDT Reset xxxx x1x1 -0-- 0000 ---- --uu 1111 1111 ---- -000 Wake-up from SLEEP xxxx xuxu -u-- uuuu ---- --uu 1111 1111 ---- -uuu
Note : uunchanged, xunknown, - unimplemented, read as "0" #value depends on the condition of the following table Condition /MCLR reset (not during sleep) /MCLR reset during sleep WDT reset (not during sleep) WDT reset during sleep Power-on reset Power-range reset 8. Instruction Set: Instruction Code 010000 00000000 010000 00000001 010000 00000010 010000 00000011 010000 00000100 010000 00000rrr 010001 1rrrrrrr 011000 trrrrrrr 111010 iiiiiiii 010111 trrrrrrr 011001 trrrrrrr 011010 trrrrrrr 011011 trrrrrrr Mnemonic Operands NOP CLRWT SLEEP TMODE RET CPIO STWR LDR LDWI I R R R, t Function No operation Clear Watchdog timer Sleep mode Return from subroutine Control I/O port register Store W to register Load register Load immediate to W Operating None 0WT TF, PF None None r None None Z None None Z None C, HC, Z 0WT, stop OSC TF, PF StackPC WCPIO WR Rt IW [R(0~3) R(4~7)] t R + 1t R + 1t W + Rt Status Status: bit 4 u 1 0 0 1 1 Status: bit 3 u 0 1 0 1 1 PSTA: bit 1 u u u u 0 u PSTA: bit 0 u u u u x 0
Load W to TMODE register WTMODE
SWAPR R, t Swap halves register INCR R, t Increment register
INCRSZ R, t Increment register, skip if zero ADDWR R, t Add W and register
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P. 12
Preliminary 2007/8
Ver1.0
MDT10P712
Instruction Code 011100 trrrrrrr 011101 trrrrrrr 011110 trrrrrrr 010010 trrrrrrr 110100 iiiiiiii 010011 trrrrrrr 110101 iiiiiiii 010100 trrrrrrr 110110 iiiiiiii 011111 trrrrrrr 010110 trrrrrrr 010101 trrrrrrr 010000 1xxxxxxx 010001 0rrrrrrr 0000bb brrrrrrr 0010bb brrrrrrr 0001bb brrrrrrr 0011bb brrrrrrr 100nnn nnnnnnnn 101nnn nnnnnnnn 110111 iiiiiiii 110001 iiiiiiii 111000 iiiiiiii 010000 00001001 Note : W WT TMODE CPIO TF PF PC : : : : : : : Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter b t : : 0 1 R: C: HC : Bit position Target : Working register : General register General register address Carry flag Half carry Mnemonic Operands Function Operating R Wt or (R+/W+1t) R 1t R 1t R Wt i WW R Wt R Wt /Rt R(n) R(n-1), CR(7), R(0)C R(n)r(n+1), CR(0), R(7)C 0W 0R 0R(b) 1R(b) Skip if R(b)=0 Skip if R(b)=1 nPC, PC+1Stack nPC W+iW Status C, HC, Z Z None Z Z Z Z Z Z Z C C Z Z None None None None None None C,HC,Z None C,HC,Z None
SUBWR R, t Subtract W from register DECR R, t Decrement register
DECRSZ R, t Decrement register, skip if zero ANDWR R, t AND W and register ANDWI i IORWR R, t IORWI i XORWI i COMR RRR RLR CLRW CLRR BCR BSR BTSC BTSS R R, b R, t R, t AND W and immediate Inclu. OR W and register
Inclu. OR W and immediate i WW Exclu. OR W and immediate i WW Rotate right register Rotate left register Clear working register Clear register Bit set
XORWR R, t Exclu. OR W and register R, t Complement register
R, b Bit clear R, b Bit Test, skip if clear R, b Bit Test, skip if set Long CALL subroutine Long JUMP to address Add immediate to W
LCALL n LJUMP n ADDWI i RTWI i
SUBWI i RTFI
Return, place immediate to StackPC,iW W Subtract W from immediate i-WW Reture from interrupt StackPC,1 GIS
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P. 13
Preliminary 2007/8
Ver1.0
MDT10P712
OSC Inclu. Exclu. AND : : : : Oscillator Inclusive `' Exclusive `' Logic AND `' Z / x i n : : : : : Zero flag Complement Don't care Immediate data ( 8 bits ) Immediate address
9. Electrical Characteristics *Note: Temperature=25C 1.Operation Current : (1) HF (C=10p) , WDT - enable , PRD - disable 4M 2.5V 3.0V 4.0V 5.0V 5.5V 420uA 560uA 950uA 1.5mA 2.4mA 10M 910uA 1.1mA 1.8mA 2.6mA 3.9mA 20M 1.5mA 2mA 3mA 4.5mA 7.3mA Sleep 6uA 10uA 20uA 30uA 50uA
These parameters are for reference only. (2) XT (C=10p) , WDT - enable , PRD - disable 1M 2.5V 3.0V 4.0V 5.0V 5.5V 140uA 180uA 360uA 730uA 1.5mA 4M 350uA 460uA 790uA 1.3mA 2mA 10M 900uA 1.1mA 1.8mA 2.6mA 3.8mA Sleep 6uA 10uA 20uA 30uA 50uA
These parameters are for reference only. (3) LF (C=10p) , WDT - enable , PRD - disable 32K 2.5V 3.0V 4.0V 5.0V 5.5V 16uA 26uA 110uA 610uA ---uA 455K 65uA 84uA 160uA 260uA 480uA 1M 90uA 140uA 240uA 360uA 630uA Sleep 6uA 10uA 20uA 30uA 50uA
These parameters are for reference only.
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P. 14
Preliminary 2007/8
Ver1.0
MDT10P712
(4) RC , WDT - enable , PRD - disable , @Vdd = 5.0V C R 4.7k 10k 3p 47k 100k 300k 470k 4.7k 10k 20p 47k 100k 300k 470k 4.7k 10k 100p 47k 100k 300k 470k 4.7k 10k 300p 47k 100k 300k 470k Freq. 8.7M 4.5M 1M 495K 167K 105K 5.1M 2.6M 580K 277K 93K 59K 2M 1M 224K 107K 36K 22K 913K 445K 98K 46K 16K 10K Current 2.3mA 1.3mA 470uA 330uA 260uA 240uA 1.4mA 840uA 370uA 300uA 260uA 250uA 710uA 470uA 280uA 250uA 240uA 240uA 450uA 320uA 240uA 230uA 220uA 220uA
These parameters are for reference only. 2. Input Voltage (Vdd = 5V) : Port Vil Vih TTL Schmitt trigger TTL Schmitt trigger Min Vss Vss 2V 3.5V Max 1V 1V Vdd Vdd
These parameters are for reference only.
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P. 15
Preliminary 2007/8
Ver1.0
MDT10P712
3. Output Voltage (Vdd = 5V) : PA,PB Voh Vol Voh Vol 3.2V 0.8V 4.3V 0.5V Condition Ioh =-20mA Iol =+20mA Ioh = -5mA Iol = +5mA
These parameters are for reference only. 4. Output Current (Max.) (Vdd = 5V) : Port A: Source current Sink current These parameters are for reference only. Port B: Source current Sink current These parameters are for reference only. 5. The basic WDT time-out cycle time : Time 2.5V 3.0V 4.0V 5.0V 24ms 22ms 20ms 18ms Current 25mA 25mA Current 25mA 25mA
5.5V 17ms These parameters are for reference only.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 16
Preliminary 2007/8
Ver1.0

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